Slew rate controllable system for powering electric machine

ABSTRACT

A slew rate controllable system for powering an electric machine. The system may include a plurality of power transistors operable for converting a direct current (DC) input into an alternating current (AC) output suitable for electrically powering the electric machine. The system may further include a gate drive system operable for controlling a slew rate associated with transitioning the power transistors between the opened and closed states.

INTRODUCTION

The present disclosure relates to systems configured for powering anelectric machine, such as but not necessarily limited to a slew ratecontrollable system configured for managing transitions of powerswitches operating to provide electrical power to a traction motor of anelectric vehicle.

In a power inversion process, pulse width modulation, pulse densitymodulation, delta-sigma modulation, pulse-frequency modulation, or otherapplication-suitable binary (on/off) switching control signals may beemployed to facilitate transitioning switches between different statesfor purposes of powering an electric machine. The control signals, forexample, may alternate a conducting state of the switches to generateelectrical power having an AC voltage waveform. Some of the more commonswitches used in higher power applications, such as those used forelectrically powering a traction motor of an electric vehicle, may bevoltage and/or current controlled between states. A wide bandgap (WBG),GaN, SiC, and other semiconductors, such as metal oxide field-effecttransistor (MOSFET) and the insulated-gate bipolar transistor (IGBT)semiconductors may form a class of switches capable of supporting a widevariety of switching events. The rate, speed, timing, etc. of theswitching events, or more specifically the transitioning of the switchesbetween on and off or opened and closed states, may be characterized asa slew rate. Depending on a type of electric machine being powered, suchas for example when powering a traction motor used for propelling anelectric vehicle, an ability to finely select and control the slew ratemay be beneficial in minimizing second order effects, such asovervoltage spikes, electromagnetic interference (EMI) bearing current,voltage overshoot, etc.

SUMMARY

One non-limiting aspect of the present disclosure relates to a slew ratecontrollable system configured for finely selecting and controlling aslew rate for switches used in powering of an electric machine. The slewrate controllable system may be particularly beneficial in accuratelycontrolling the slew rate of power switches, transistors, etc. used infacilitating powering of a traction motor of the type commonly employedfor propelling an electric vehicle. The slew rate controllable systemmay dynamically adjust and precisely control the slew rates according toa wide variety of operating and performance and considerations toprovide differing switching speeds capable of balancing high switchingslew rates relative to performance benefits and the operatingenvironment.

One non-limiting aspect of the present disclosure relates to a slew ratecontrollable system for powering an electric machine. The system mayinclude a plurality of power transistors operable for converting adirect current (DC) input into an alternating current (AC) outputsuitable for electrically powering the electric machine. The powertransistors may be operable between an opened state and a closed stateto facilitate generating the AC outputs. The system may further includea gate drive system operable for controlling a slew rate associated withtransitioning the power transistors between the opened and closedstates. The gate drive system may include a plurality of gate drivecircuits individually connected to a gate terminal of a correspondingone of the power transistors.

The gate drive system may include a gate driver operable for providingthe gate drive circuits with a control signal suitable for optimizingthe slew rate of the power transistor associated therewith.

The control signals may be operable for directing the gate drivecircuits to control a gate-source voltage (Vgs) between a gate terminaland a source terminal of the power transistor associated therewith suchthat the Vgs controls the power transistors between the opened andclosed states.

The control signals are operable for directing the gate drive circuitsto control a gate current (Ig) to a gate terminal of the powertransistor associated therewith such that the Ig controls the powertransistors between the opened and closed states.

The slew rate controllable system may include a DC link capacitorconnected between the power transistors and a DC source providing the DCinput, optionally with the control signals optimizing discharge speed ofthe DC link capacitor to avoid or minimize voltage overshoot of thepower transistors when transitioning between the opened and closedstates.

The gate driver may be configured for generating the control signals asa function of one or more of a DC voltage of the DC source, atemperature of the DC link capacitor, a current of one or more of the ACoutputs and a junction temperature, a maximum discharge time, adrain-source voltage (Vds), a voltage threshold (Vth) of one or more ofthe power transistors.

The gate drive circuits may include an upper drive switch, an upperresistor, a lower resistor and a lower switch, the upper resistor andthe lower resistor connecting in series between the upper drive switchand the lower driver switch, optionally with the gate terminalassociated therewith connecting between a lower side of the upperresistor and an upper side of the lower resistor.

The gate drive system may include an upper voltage source and a lowervoltage source for each of the gate drive circuits, optionally with theupper voltage source connected to the upper switch and the lower voltagesource connected to the lower switch associated therewith.

The gate drive circuits provide a gate voltage to the gate terminalassociated therewith, optionally the gate voltage being proportional toa voltage difference between the upper and lower voltage sources andresistances of the upper and lower resistors.

The control signals may be configured to selectively control the upperand lower switches between opened and closed states to set the gatevoltages and thereby the slew rate of the power transistor associatedtherewith.

The control signals may be pulse width modulated (PWM) signals operablebetween a high voltage and a low voltage, optionally the high voltagetransitioning the upper or lower switch in receipt thereof to the openedstate and the low voltage transitioning the upper or lower switch inreceipt thereof to the closed state.

The gate driver may selectively vary a duty cycle for the PWM signals tocontrol the slew rate of the power transistor associated therewith.

The gate drive circuits may include an upper voltage source, a lowervoltage source, an upper switch, a lower switch and an upper resistor,optionally with the upper switch connecting in series with the uppervoltage source and to an upper side of the upper resistor, the lowerswitching connecting in series with the lower voltage source and a lowerside of the upper resistor, the gate terminal associated therewithconnecting to the lower side of the upper resistor.

The gate drive circuits may include an upper voltage source, a lowervoltage source, an upper switch, a lower switch and a lower resistor,optionally with the upper switch connecting in series with the uppervoltage source and to an upper side of the lower resistor, the lowerswitching connecting in series with the lower voltage source and a lowerside of the lower resistor, the gate terminal associated therewithconnecting to the upper side of the lower resistor.

One non-limiting aspect of the present disclosure relates to a slew ratecontrollable system for powering a traction motor of a vehicle. Thesystem may include a plurality of power switches operable for convertinga direct current (DC) input into an alternating current (AC) outputsuitable for electrically powering the traction motor. The powerswitches may be operable between an opened state and a closed state tofacilitate generating the AC outputs. The system may further include agate drive system operable for controlling a slew rate associated withtransitioning the power switches between the opened and closed states,optionally with a plurality of gate drive circuits individuallyconnected to a gate terminal of a corresponding one of the powerswitches and operable for controlling a gate-source voltage (Vgs)between a gate terminal and a source terminal of the power switchassociated therewith, with the Vgs controlling the power switchesbetween the opened and closed states.

The gate drive circuits may include an upper voltage source, a lowervoltage source, an upper switch, an upper resistor and a lower resistor,the upper switch connecting in series with the upper voltage source, theupper resistor, the lower resistor, and the lower voltage source,optionally with the gate terminal associated therewith connected betweena lower side of the upper resistor and an upper side of the lowerresistor.

The gate drive system may be configured for generating control signalsto set the Vgs of each gate drive circuit by correspondingly controllingthe upper and lower switches between opened and closed states.

The gate drive system may be configured to determine the control signalsas a function of one or more of a DC voltage of the DC input, atemperature of a DC link capacitor connected across the DC source, acurrent of one or more of the AC outputs and a junction temperature, amaximum discharge time, a drain-source voltage (Vds) or a voltagethreshold (Vth) of one or more of the power switches.

One non-limiting aspect of the present disclosure relates to a slew ratecontrollable system for powering a traction motor of a vehicle. Thesystem may include a plurality of power switches operable for convertinga direct current (DC) input into an alternating current (AC) outputsuitable for electrically powering the traction motor. The powerswitches may be operable between an opened state and a closed state tofacilitate generating the AC outputs. The system may include a gatedrive system operable for controlling a slew rate associated withtransitioning the power switches between the opened and closed states,optionally with a plurality of gate drive circuits individuallyconnected to a gate terminal of a corresponding one of the powerswitches, the gate drive circuits being operable for controlling a gatecurrent (Ig) to a gate terminal of the power switch associatedtherewith, with the Ig controlling the power switches between the openedand closed states.

The slew rate controllable system may include a DC link capacitorconnected between the power switches and a DC source providing the DCinput such that the gate drive system is operable for controlling theslew rates of the power switches to optimize discharge speed of the DClink capacitor to avoid or minimize voltage overshoot when transitioningbetween the opened and closed states.

These features and advantages, along with other features and advantagesof the present teachings, may be readily apparent from the followingdetailed description of the modes for carrying out the present teachingswhen taken in connection with the accompanying drawings. It should beunderstood that even though the following figures and embodiments may beseparately described, single features thereof may be combined toadditional embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which may be incorporated into and constitutea part of this specification, illustrate implementations of thedisclosure and together with the description, serve to explain theprinciples of the disclosure.

FIG. 1 illustrates a partial schematic view of a slew rate controllablesystem in accordance with one non-limiting aspect of the presentdisclosure.

FIG. 2 illustrates a partial schematic view of a gate drive circuit inaccordance with one non-limiting aspect of the present disclosure.

FIG. 3 illustrates a graph controlled slew rates in accordance with onenon-limiting aspect of the present disclosure.

FIG. 4 illustrates a partial schematic view of one of the gate drivecircuits omitting the lower resistor in accordance with one non-limitingaspect of the present disclosure.

FIG. 5 illustrates a partial schematic view of one of the gate drivecircuits omitting the upper resistor in accordance with one non-limitingaspect of the present disclosure.

DETAILED DESCRIPTION

As required, detailed embodiments of the present disclosure may bedisclosed herein; however, it may be understood that the disclosedembodiments may be merely exemplary of the disclosure that may beembodied in various and alternative forms. The figures may not benecessarily to scale; some features may be exaggerated or minimized toshow details of particular components. Therefore, specific structuraland functional details disclosed herein may need not to be interpretedas limiting, but merely as a representative basis for teaching oneskilled in the art to variously employ the present disclosure.

FIG. 1 illustrates a partial schematic view of a slew rate controllablesystem 10 in accordance with one non-limiting aspect of the presentdisclosure. The system 10 may include a gate drive system 12 operablefor powering an electric machine 14, which for exemplary purposes ispredominantly described as an electric motor 14, typically referred toas a traction motor 14. The electric motor 14 may be of the typeemployed within a vehicle, such as an electric vehicle, to providemechanical, tractive force operable for propelling the vehicle orotherwise performing work. As described in greater detail below, thegate drive system 12 may be operable for finely selecting andcontrolling a slew rate for a plurality of power switches, transistors,etc. S1, S2, . . . S6 used as part of a power inverter module (PIM) 16to facilitate powering the electric machine 14. The system 12 maydynamically adjust and precisely control the slew rates according to awide variety of operating and performance considerations to providediffering switching speeds capable of balancing high switching slewrates relative to performance benefits and the operating environment.While predominately described with respect to selectively controllingslew rates for switches S1, S2, . . . S6 used in an electric vehicle,one skilled in the art would readily recognize the capabilities of thesystem 12 being advantageous in facilitating powering other types ofelectric machines 14 that would similarly benefit from minimizing secondorder effects, such as overvoltage spikes, electromagnetic interference(EMI) bearing current, voltage overshoot, etc.

The vehicle may include a rechargeable energy storage system (RESS) 20for storing and supplying electrical power for various systems includedonboard the vehicle. The RESS 20 may be a battery or other energystorage device capable of selectively supplying electrical power to andreceiving electrical power from the electric machine 14 via the PIM 16.When powering the electric machine 14, the RESS 20 may be configured asa source for providing a direct current (DC) input 22 to the PIM 16. ADC link capacitor 24 may be disposed therebetween to smooth, filter, andotherwise process the DC input 22 for use with the PIM 16. The PIM 16 isshown to include six power transistors/switches S1, S2, . . . S6, eachhaving a gate terminal G, a drain terminal D, and a source terminal S.The gate terminal G of each switch S1, S2, . . . S6 may each beseparately and independently connected to one of a plurality of gatedrive circuits 26. The switches S1, S2, . . . S6 may corresponding witha broad range of switches S1, S2, . . . S6, including wide bandgap(WBG), GaN, SiC, and other similar semiconductors, such as metal oxidefield-effect transistor (MOSFET) and the insulated-gate bipolartransistor (IGBT) semiconductors. The gate drive system 12 may include agate controller 30 operable for individually and specificallycontrolling the gate drive circuits 26 to control a rate, speed, timing,etc. of switching events for the switches S1, S2, . . . S6, i.e., tocontrol transitioning of the switches S1, S2, . . . S6 between on andoff or opened and closed states. The transitioning of the switches S1,S2, . . . S6 between states may be characterized as a slew rate, withthe gate drive circuits 26 being operable to individually select theslew rate for each of the switches S1, S2, . . . S6 according tocorresponding control signals 32 provided from the gate controller 30.One non-limiting aspect of the present disclosure contemplates the gatedrive circuits 26 being operable for providing a gate voltage and/or agate current to the gate terminal G associated therewith, with thecorresponding gate voltage or gate current being operable to transitionthe associate switch S1, S2, . . . S6 between opened and closed states,i.e., to control whether the corresponding switch S1, S2, . . . S6 isactive or inactive.

The gate controller 30 may include a gate driver 34 configured forindividually providing the control signals 32 to each of the gate drivecircuits 26. The gate driver 34 may be used in this manner to facilitateswitching events for the switches S1, S2, . . . S6 whereby the DC input22 may be converted to an alternating current (AC) output 38. The ACoutput 38 may be generated in the illustrated manner to provide apolyphase output having a plurality of AC signals 40, 42, 44 suitablefor use in powering the electric machine 14, which are shown fornon-limiting purposes to correspond with a three-phase implementationwhere a three-phase AC output 38 is provided to an AC bus or windings ofthe electric machine 14, such as via a corresponding input terminal forthe associated AC input. As noted above, the use of the gate drivesystem 12 to facilitate a controllable slew rate based methodology forcontrolling switching events, and thereby conversion of a DC input 22 toAC outputs 38 suitable for powering the electric machine 14 is presentedfor non-limiting purposes as the present disclosure fully contemplatesthe gate drive system 12 being operable in other environments and forother purposes. The present disclosure, as such, fully contemplates useof the gate drive system 12 to control slew rates for switches S1, S2, .. . S6 or other devices in addition to the illustrated use case wherethe switches S1, S2, . . . S6 may be configured to operate as aunidirectional or bidirectional DC/AC converter.

The gate controller 30 may include a non-transitory computer-readablestorage medium having a plurality of non-transitory instructions storedthereon, which when executed with an associated one or more processors,may be operable in accordance with the present disclosure to facilitategenerating the control signals 32 in a manner that provides a desirableslew rate while also managing the AC outputs needed for proper poweringof the electric machine 14. While not shown in individual detail, aplurality of sensors or other features may be employed to facilitatemeasuring or otherwise determining a DC voltage of the DC source 20, atemperature of the DC link capacitor 24, a current of one or more of theAC outputs 38, and a junction temperature, a maximum discharge time, adrain-source voltage (Vds), a voltage threshold (Vth) of one or more ofthe switches/power transistors S1, S2, . . . S6. The gate controller 30may process the sensor measurements, metrics, etc. to determine adesirable slew rate for each of the switches S1, S2, . . . S6, which mayinclude selecting the control signals 32 to optimize a discharge speedof the DC link capacitor 24 to avoid or minimize voltage overshoot forthe switches S1, S2, . . . S6 when transitioning between the opened andclosed states. The gate controller 30 may be used in this manner tochange slew rates of the switches S1, S2, . . . S6 in real-time, withinand between switching events, and optionally in an isolated manner toalter slew rates to be selected based upon operating conditions, desiredperformance, etc.

FIG. 2 illustrate a partial schematic view of one of the gate drivecircuits 26 in accordance with one non-limiting aspect of the presentdisclosure. While the connection would be repeated separately for eachswitch S1, S2, . . . S6, the gate drive circuit 26 is shown forexemplary purpose as connected to a gate terminal G of the switch S1.The gate drive circuit 26 is shown in this manner as connectable to thegate terminal G due to the switch S1 being configured as a voltageand/or current controlled type of switch S1 whereby a gate voltageand/or a gate current provided to the gate terminal G may be used totransition the switch S1 between opened and closed states, i.e., tocontrol switching events. In the event the switch S1 employed analternative configuration, the gate drive circuit 26 may be similarlyadapted to provide voltage and/or current to the corresponding terminal.The gate drive circuit 26 may include an upper gate switch 46, an upperresistor 48, a lower resistor 50, and a lower gate switch 52, with theupper gate switch 46 being driven with an upper voltage source 58 andthe lower gate switch 52 being driven with a lower voltage source 60.The upper gate switch 46 is shown to be connected in series with theupper voltage source 58, the upper resistor 48, the lower resistor 50,and the lower voltage source 60, with the upper gate switch 46 connectedbetween the upper voltage source 58 and an upper side of the upperresistor 48, the gate terminal G connected between a lower side of theupper resistor 48 and an upper side of the lower resistor the upper sideof the lower resistor 50 connected to the lower side of the upperresistor 48, and the lower gate switch 52 connected between the lowervoltage source 60 and a lower side of the lower resistor 50.

The gate driver 34 may be configured to generate the control signals 32with separate control signals 62, 64 suitable for selectively openingand closing the upper and lower gate switches 46, 52, and thereby,controlling the gate voltage and/or current provided to the gateterminal G. The control signals 62, 64 may correspond with pulse widthmodulated (PWM) signals operable between a high voltage H and a lowvoltage L to correspondingly control the upper and lower gate switches46, 52 to a closed state and an opened state. A duty cycle of thecontrol signals 32 may be varied to finely adjust the gate voltageand/or current at precise levels depending on the desired slew rate,e.g., to facilitate adjusting the slew rate in real-time according todesired operation of the electric machine 14. The PWM duty cycle controlmay be used to change the output current in and out of the switch's gateG (capacitor). The fastest gate speed and slew rates may be preferredfor switching due to lag and energy consideration. A method thatcontrols the PWM duty cycle may be based upon the DC bus voltage andcurrent to allow optimal efficiency and reliability. For 400-800V system12, for example, the present disclosure may be used to adapt the PIM 16for each bus. In the illustrated configuration, the control signals 62,64 may be operable for directing the gate drive circuits 26 to control agate-source voltage (Vgs) between the gate terminal G and the sourceterminal of the switch S1, with the Vgs controlling the powertransistors between the opened and closed states, and/or the controlsignals 62, 64 may be operable for directing the gate drive circuits 26to control a gate current (Ig) to the gate terminal G, with the Igcontrolling the power transistors between the opened and closed states.The Vgs and Ig provided to the gate terminal G may be proportional to avoltage difference between the upper and lower voltage sources 58, 60and resistances of the upper and lower resistors 48, 50.

The gate driver 34 may be configured for providing the upper and lowergate switches 46, 52 differing control signals 32, such as inillustrated manner whereby the control signals 32 may have differingduty cycles. This capability for individually varying the duty cycle orother aspects of the control signals 32 used to transition the upper andlower gate switches 46, 52 between states may be beneficial in enablingthe gate controller 30 to control Vgs and/or Ig with a very fine andprecise level of granularity, with the resulting voltage and currentbeing set according to the upper and lower voltage sources 58, 60 andresistivity of the upper or lower resistors 48, 50. The gate controller30 may optionally control the voltages provided with each of the upperand lower voltage sources 58, 60 to further enhance its capabilities forfinely selecting the voltage and/or the current being provided to thegate terminal G. In some circumstances, for example, the control signals32 may be used to selectively open or deactivate either one of the upperand lower gate switches 46, 52, optionally in concert with varying thevoltages of the upper and lower voltage sources 58, 60, so as to therebyeven further add to the specificity in selecting and achieving thedesired slew rate.

FIG. 3 illustrates a graph 70 for a method of controlling slew rate inaccordance with one non-limiting aspect of the present disclosure. Thegraph 70 is shown to include a vertical axis 72 for voltage and currentand a horizontal axis 74 for time. A first waveform 78 representsvoltage between the drain and source terminals (Vds), a second waveform80 represents current through the drain terminal (Id), a third waveform82 represents Vgs, and a fourth waveform 84 represents Ig. The graph 70illustrates an exemplary scenario whereby the slew rate of the switchS1, i.e., dV/dt and/or dI/dt, may be selectively controlled according totransitional properties of the switch S1. The period occurring prior totime T0 may correspond with the switch S1 being off or an activewhereafter at time T0 the gate drive circuit 26 begins powering the gateterminal G at an initial slew rate. From time T0 to time T1 the initialslew rate may be maintained while Id increases. At approximately timeT1, or slightly thereafter as the slope of Vgs lessens and/or as Vdsdrops, the D drive circuit may begin powering the gate terminal G at anintermediary slew rate, which may be useful in controlling a slope or arate at which Vds correspondingly decreases. At approximately time T2,or once Vds reaches or approaches its minimum, a final or greater slewmay be implemented. The capability to selectively control Vgs and/or Igduring transitioning of the switch S1 may be beneficial in maximizingperformance, or more particular the slew rate, as the switch S1progresses through various states associated with transitioning from anopen state to a closed state. The method may proceed in this mannerwhereby the slew rate for the drive circuits 26 and the attendanttransitioning of the connected to switches S1, S2, . . . S6 may beimplemented to control the DC to AC conversion needed for powering theelectric machine 14.

FIG. 4 illustrates a partial schematic view of one of the gate drivecircuits 26 omitting the lower resistor 50 in accordance with onenon-limiting aspect of the present disclosure. FIG. 5 illustrates apartial schematic view of one of the gate drive circuits 26 omitting theupper resistor 48 in accordance with one non-limiting aspect of thepresent disclosure. These alternative configurations for the gate drivecircuits 26 may be illustrative of capabilities for the presentdisclosure to minimize or reduce the quantity of circuit componentswhile still maintaining desirable levels of slew rate control. While notshown, the present disclosure additionally contemplates similarlyomitting the upper and/or lower switches 46, 52. Each of the drivecircuits 26 shown in FIGS. 2, 4 , and/or 5 may be simultaneouslyemployed, e.g., some of the switches S1, S2, . . . S6 may be connectedto one type of drive circuit 26 while one or more the other switches S1,S2, . . . S6 are connected to drive circuits 26 having a differingconfiguration. This capability may further enhance the beneficialcontrol of slew rates in the manner contemplated herein.

As supported above, the present disclosure relates to a system andmethod to achieve real-time slew rate (SR) control of power transistorsfor inverters and converters. It may include minimal amounts of hardwareas a voltage/current source and a low-voltage switch, with pulsemodulation to control the gate current to realize numerous slew rates.This may equivalently transform the gate drive circuit into a chargepump for the gate capacitor, enabling advantageous methods of controlthrough variable-speed gate drive circuits allowing fine tuning ofswitching performance to optimize between loss, overshoot, EMI, andbearing current. In this manner, the gate drive circuits may be operablefor turning on/off the power switches to converter electrical powerbetween DC and AC, optionally with faster switching, minimal switchingloss and improved max power capability, thereby limiting the effects ofelectrical stress on power switches, ringing, conductive and radiatedEMI, and motor terminal voltage overshoot (PDIV) and bearing current.The gate drive system may include the following design features: pulsemodulation control to change transistor switching slew rates inreal-time, and between and within the switching events; applicabilityfor voltage-source and current-source based or hybrid gate drives;feedforward control using look up tables (LUTs) to alter slew rate basedupon operating conditions, i.e. Vdc, current, Vth, and junctiontemperature; feedback control based upon operation conditions,transistor signal sensing, and part-to-part variation and degradation;tune pulse modulation control at max junction temperature for ontransient, and at min junction temperature for off transient; slew ratecontrol to compensate for transistor/switch part-to-part variations,i.e. Vth, gate resistor, stray inductance; class-D topology for thepulse-modulation based gate drive system; modulation control to controlslew rate to realize capacitor discharge while managing the I/Vovershoots; slew rate control for switching ON/OFF solid-state relay(SSR)/E-fuse to manage the I/V overshoots and protect cap and battery;slew rate control to increase loss for BEV-HEAT and reduce soft turn-offtime when switch short circuit; control to regulate dI/dt to preventsecondary effects of changing dV/dt; make EMI frequency featureconstant; and/or high-voltage discharge by keeping one side of switcheson and PWM the other side of switches on the side (high-side orlow-side) with the PWM-based slew rate control to manage voltageovershoot.

The terms “comprising”, “including”, and “having” are inclusive andtherefore specify the presence of stated features, steps, operations,elements, or components, but do not preclude the presence or addition ofone or more other features, steps, operations, elements, or components.Orders of steps, processes, and operations may be altered when possible,and additional or alternative steps may be employed. As used in thisspecification, the term “or” includes any one and all combinations ofthe associated listed items. The term “any of” is understood to includeany possible combination of referenced items, including “any one of” thereferenced items. “A”, “an”, “the”, “at least one”, and “one or more”are used interchangeably to indicate that at least one of the items ispresent. A plurality of such items may be present unless the contextclearly indicates otherwise. All values of parameters (e.g., ofquantities or conditions), unless otherwise indicated expressly orclearly in view of the context, including the appended claims, are to beunderstood as being modified in all instances by the term “about”whether or not “about” actually appears before the value. A componentthat is “configured to” perform a specified function is capable ofperforming the specified function without alteration, rather than merelyhaving potential to perform the specified function after furthermodification. In other words, the described hardware, when expresslyconfigured to perform the specified function, is specifically selected,created, implemented, utilized, programmed, and/or designed for thepurpose of performing the specified function.

While various embodiments have been described, the description isintended to be exemplary, rather than limiting and it will be apparentto those of ordinary skill in the art that many more embodiments andimplementations are possible that are within the scope of theembodiments. Any feature of any embodiment may be used in combinationwith or substituted for any other feature or element in any otherembodiment unless specifically restricted. Accordingly, the embodimentsare not to be restricted except in light of the attached claims andtheir equivalents. Also, various modifications and changes may be madewithin the scope of the attached claims. Although several modes forcarrying out the many aspects of the present teachings have beendescribed in detail, those familiar with the art to which theseteachings relate will recognize various alternative aspects forpracticing the present teachings that are within the scope of theappended claims. It is intended that all matter contained in the abovedescription or shown in the accompanying drawings shall be interpretedas illustrative and exemplary of the entire range of alternativeembodiments that an ordinarily skilled artisan would recognize asimplied by, structurally and/or functionally equivalent to, or otherwiserendered obvious based upon the included content, and not as limitedsolely to those explicitly depicted and/or described embodiments.

What is claimed is:
 1. A slew rate controllable system for powering anelectric machine, comprising: a plurality of power transistors operablefor converting a direct current (DC) input into an alternating current(AC) output suitable for electrically powering the electric machine, thepower transistors operable between an opened state and a closed state tofacilitate generating the AC output; and a gate drive system operablefor controlling a slew rate associated with transitioning the powertransistors between the opened and closed states, the gate drive systemincluding a plurality of gate drive circuits individually connected to agate terminal of a corresponding one of the power transistors.
 2. Theslew rate controllable system according to claim 1, wherein: the gatedrive system includes a gate driver operable for providing the gatedrive circuits with a control signal suitable for optimizing the slewrate and controlling the power switches to generate the AC output. 3.The slew rate controllable system according to claim 2, wherein: thecontrol signals are operable for directing the gate drive circuits tocontrol a gate-source voltage (Vgs) between a gate terminal and a sourceterminal of the power transistor associated therewith, the Vgscontrolling the power transistors between the opened and closed states.4. The slew rate controllable system according to claim 2, wherein: thecontrol signals are operable for directing the gate drive circuits tocontrol a gate current (Ig) to a gate terminal of the power transistorassociated therewith, the Ig controlling the power transistors betweenthe opened and closed states.
 5. The slew rate controllable systemaccording to claim 2, further comprising: a DC link capacitor connectedbetween the power transistors and a DC source providing the DC input,the control signals optimizing discharge speed of the DC link capacitorto avoid or minimize voltage overshoot of the power transistors whentransitioning between the opened and closed states.
 6. The slew ratecontrollable system according to claim 5, wherein: the gate driver isconfigured for generating the control signals as a function of one ormore of a DC voltage of the DC source, a temperature of the DC linkcapacitor, a current of one or more of the AC output and a junctiontemperature, a maximum discharge time, a drain-source voltage (Vds), avoltage threshold (Vth) of one or more of the power transistors.
 7. Theslew rate controllable system according to claim 2, wherein: the gatedrive circuits include an upper drive switch, an upper resistor, a lowerresistor and a lower switch, the upper resistor and the lower resistorconnecting in series between the upper drive switch and the lower driverswitch, with the gate terminal associated therewith connecting between alower side of the upper resistor and an upper side of the lowerresistor.
 8. The slew rate controllable system according to claim 7,wherein: the gate drive system includes an upper voltage source and alower voltage source for each of the gate drive circuits, with the uppervoltage source connected to the upper switch and the lower voltagesource connected to the lower switch associated therewith.
 9. The slewrate controllable system according to claim 8, wherein: the gate drivecircuits provide a gate voltage to the gate terminal associatedtherewith, the gate voltage being proportional to a voltage differencebetween the upper and lower voltage sources and resistances of the upperand lower resistors.
 10. The slew rate controllable system according toclaim 9, wherein: the control signals are configured to selectivelycontrol the upper and lower switches between opened and closed states toset the gate voltages and thereby the slew rate of the power transistorassociated therewith.
 11. The slew rate controllable system according toclaim 10, wherein: the control signals are pulse width modulated (PWM)signals operable between a high voltage and a low voltage, the highvoltage transitioning the upper or lower switch in receipt thereof tothe opened state and the low voltage transitioning the upper or lowerswitch in receipt thereof to the closed state.
 12. The slew ratecontrollable system according to claim 11, wherein: the gate driverselectively varies a duty cycle for the PWM signals to control the slewrate of the power transistor associated therewith.
 13. The slew ratecontrollable system according to claim 2, wherein: the gate drivecircuits includes an upper voltage source, a lower voltage source, anupper switch, a lower switch and an upper resistor, the upper switchconnecting in series with the upper voltage source and to an upper sideof the upper resistor, the lower switching connecting in series with thelower voltage source and a lower side of the upper resistor, the gateterminal associated therewith connecting to the lower side of he upperresistor.
 14. The slew rate controllable system according to claim 2,wherein: the gate drive circuits includes an upper voltage source, alower voltage source, an upper switch, a lower switch and a lowerresistor, the upper switch connecting in series with the upper voltagesource and to an upper side of the lower resistor, the lower switchingconnecting in series with the lower voltage source and a lower side ofthe lower resistor, the gate terminal associated therewith connecting tothe upper side of the lower resistor.
 15. A slew rate controllablesystem for powering a traction motor of a vehicle, comprising: aplurality of power switches operable for converting a direct current(DC) input into an alternating current (AC) output suitable forelectrically powering the traction motor, the power switches operablebetween an opened state and a closed state to facilitate generating theAC outputs; and a gate drive system operable for controlling a slew rateassociated with transitioning the power switches between the opened andclosed states, the gate drive system including a plurality of gate drivecircuits individually connected to a gate terminal of a correspondingone of the power switches, the gate drive circuits being operable forcontrolling a gate-source voltage (Vgs) between a gate terminal and asource terminal of the power switch associated therewith, the Vgscontrolling the power switches between the opened and closed states. 16.The slew rate controllable system according to claim 15, wherein: thegate drive circuits include an upper voltage source, a lower voltagesource, an upper switch, an upper resistor and a lower resistor, theupper switch connecting in series with the upper voltage source, theupper resistor, the lower resistor, and the lower voltage source, withthe gate terminal associated therewith connected between a lower side ofthe upper resistor and an upper side of the lower resistor.
 17. The slewrate controllable system according to claim 16, wherein: the gate drivesystem is configured for generating control signals to set the Vgs ofeach gate drive circuit by correspondingly controlling the upper andlower switches between opened and closed states.
 18. The slew ratecontrollable system according to claim 17, wherein: the gate drivesystem is configured to determine the control signals as a function ofone or more of a DC voltage of the DC input, a temperature of a DC linkcapacitor connected across the DC source, a current of one or more ofthe AC outputs and a junction temperature, a maximum discharge time, adrain-source voltage (Vds) or a voltage threshold (Vth) of one or moreof the power switches.
 19. A slew rate controllable system for poweringa traction motor of a vehicle, comprising: a plurality of power switchesoperable for converting a direct current (DC) input into an alternatingcurrent (AC) output suitable for electrically powering the tractionmotor, the power switches operable between an opened state and a closedstate to facilitate generating the AC outputs; and a gate drive systemoperable for controlling a slew rate associated with transitioning thepower switches between the opened and closed states, the gate drivesystem including a plurality of gate drive circuits individuallyconnected to a gate terminal of a corresponding one of the powerswitches, the gate drive circuits being operable for controlling a gatecurrent (Ig) to a gate terminal of the power switch associatedtherewith, the Ig controlling the power switches between the opened andclosed states.
 20. The slew rate controllable system according to claim19, further comprising: a DC link capacitor connected between the powerswitches and a DC source providing the DC input, wherein the gate drivesystem is operable for controlling the slew rates of the power switchesto optimize discharge speed of the DC link capacitor to avoid orminimize voltage overshoot when transitioning between the opened andclosed states.